1. Technical Field
The disclosure relates generally to integrated circuit (IC) chip fabrication, and more particularly, to a through via in an ultra high resistivity wafer and related methods.
2. Background Art
A vertical stacking method to integrate multiple chips on a two-dimensional (2-D) or three-dimensional (3-D) package may need the use of through vias to reduce the interconnect delay and maximize circuit performance. In conventional approaches, a through via is formed through a whole wafer of a chip, and thus can only be positioned by the sides of devices on the wafer. As a consequence, the issue of alignment hampers via formation and chip stacking processes.
Radio frequency (RF) SOI technology requires ultra high resisitivity wafers to deal with insertion loss. In many situations, it is preferable that a chip maintains the ultra high resisitivity on the top surface while having lowered resisitivity on the bottom surface. There is no satisfactory solution for this in the conventional technologies.